Digital structures for high-speed signal processing

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  • Autor: Maciej Czyżak
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Digital structures for high-speed signal processing
Seria: Monografie nr 141

rok wydania: 2013
ISBN: 978-83-7348-505-1

CONTENTS
LIST OF IMPORTANT SYMBOLS AND ACRONYMS / 7
1. INTRODUCTION / 11
1.1. Motivation and subject of the work / 12
1.2. Contents of the dissertation / 13
2. REVIEW OF THE FIELD OF DIGITAL SIGNAL PROCESSING / 17
2.1. Signal processing and digital signal processing / 17
2.2. General structure of DSP systems / 19
2.2.1. Exemplary structures of signal processing systems / 19
2.2.2. Basic structure of DSP systems / 20
2.3. A note on arithmetic operations in DSP / 22
2.4. Summary / 25
3. CRITICAL REVIEW AND ANALYSIS OF SELECTED RESIDUE NUMBER SYSTEMS / 27
3.1. A note on number systems / 27
3.2. Residue number systems / 28
3.3. Selected residue number systems / 30
3.3.1. Polynomial mappings / 30
3.3.2. Quadratic Residue Number System / 31
3.3.3. Modified Quadratic Residue Number System / 32
3.3.4. Quadratic-Like Residue Number System / 34
3.3.5. Flexible Modulus Residue Number System / 37
3.3.6. Polynomial Residue Number System / 38
3.3.7. Moduli Replication Residue Number System / 39
3.3.8. Algebraic Integer Residue Number System / 44
3.4. Core function / 46
3.5. Index calculus in GF(m) / 47
3.6. Zech logarithms / 48
3.7. Summary / 49
4. BINARY-TO-RESIDUE CONVERSION / 50
4.1. Introduction / 50
4.2. Binary-to-residue conversion / 54
4.3. Preprocessing stage / 55
4.3.1. Segmentation of input word / 55
4.3.2. Evaluation of segmentation effects for five-bit moduli / 56
4.3.3. Structures of Segment Modulo Generators / 58
4.3.4. Simplification of preprocessing stage using common terms of neighbouring segments / 60
4.4. Pipelined Two-Operand Modulo Adders / 61
4.4.1. Pipelined TOMA based on Ripple-Carry Adder / 62
4.4.2. Pipelined TOMA based on Parallel-Prefix Adder / 67
4.4.3. Pipelined TOMA based on Hiasat two-operand modulo adder / 72
4.4.4. New five-bit TOMA / 76
4.5. Multi-operand modulo adders / 80
4.6. Final Modulo Generators /  85
4.7.B/RNS converter based on Unified Channel Structure / 86
4.8.B/RNS converter based on Per (m) approach / 92
Contents 4
4.9. Comparison of approaches based on UCS and Per(m) / 97
4.10. Two's Complement System TCS/RNS converter / 98
4.10.1. Conversion of signed binary numbers to RNS / 98
4.10.2. Algorithm of TCS/RNS conversion / 99
4.10.3. Architecture of TCS/RNS converter / 100
4.11. Summary / 104
5. RESIDUE-TO-BINARY CONVERSION / 106
5.1. Introduction and review / 106
5.2. RNS/B converter based on CRT and CSA tree output reduction / 108
5.3. RNS/B converter based on magnitude index calculation / 116
5.4. RNS/B converter with quasi-regular structure based on CRT / 122
5.5. RNS/B converter based on core function / 130
5.5.1. Basic properties of core function and the principle of new B/RNS conversion / 130
5.5.2. RNS/B conversion algorithm and converter architecture / 133
5.6. Summary / 137
6. FAST MODULAR MULTIPLICATION FOR SMALL MODULI / 140
6.1. Introduction / 140
6.2. Basic blocks of five-bit Modular Multipliers (MMs) / 140
6.3. Basic architectures of five-bit MMs / 143
6.4. Architecture of new five-bit MM / 146
6.5. Design of five-bit MMs by a constant / 149
6.6. Comparison of five-bit MMs / 150
6.7. Summary / 151
7. RESIDUE SCALING AND SMALL RANGE NON-ITERATIVE RESIDUE DIVISION / 152
7.1. Introduction / 152
7.2. Scaling basics / 154
7.3. Fast parallel scaling based on magnitude index computation / 156
7.3.1. Scaling algorithm / 156
7.3.2. Scaling error evaluation and reduction / 159
7.3.3. Scaler architecture / 161
7.3.4. Scaler hardware amount and delay evaluation / 163
7.4. Scaling of signed residue numbers based on MRS / 166
7.5. Scaling of signed numbers based on the CR / 169
7.5.1. Error impact analysis of approximate CRT conversion / 170
7.5.2. Scaling with the use of approximate projections / 171
7.5.3. Scaler architecture / 174
7.5.4. Analysis of scaler hardware amount and delay / 174
7.6. Improved non-iterative residue division for small number ranges / 177
7.6.1. Multiplicative residue division algorithm / 178
7.6.2. Improved multiplicative residue division algorithm / 179
7.7. Summary / 182
8. SELECTED RESIDUE NUMBER SYSTEM APPLICATIONS FOR FAST DIGITAL SIGNAL PROCESSING / 183
8.1. TCS//RNS converter / 183
8.2. RNS/B converter / 185
8.3. Residue scaler / 187
8.4. Residue divider / 187
8.5. RNS FIR filter / 191
8.6. FFT pipelined processor based on the modified quadratic residue number system / 195
8.7. Example of spectral analysis of transformer inrush and short-circuit currents with radix-4 MQRNS FFT processor / 205
Contents 5
8.7.1. Introduction / 205
8.7.2. Theoretical analysis of transformer inrush current / 206
8.7.3. Theoretical analysis of transformer short-circuit current / 209
8.7.4. On-line spectral analysis / 209
8.8. Summary / 213
9. SUMMARY AND CONCLUSIONS / 214
Summary in English / 217
Summary in Polish / 217
Appendix 1. Segmentation results for m = 17, 19, 23, 25, 27 and the chosen wordlength of input words l = 12, 14, 16, 24, 32 and
b = 1, 2, 3, 4 / 218
Appendix 2. Exemplary synthesis results for multipliers by a constant / 222
Appendix 3. A note on origin and the initial period of digital signal processing / 244
REFERENCES / 247